In many applications for semiconductor memory circuits there is only a limited supply of power available, generally a battery. In other applications the supply of power is not a limiting factor but the heat generated by an integrated circuit must be reduced to a minimum. It is in the practice to "power down" memory circuits when they are not in use to reduce the overall power consumption of a memory system.
In NMOS memory circuits, transistors with very low threshold voltages, low V.sub.t devices, have been used to power switch the positive power supply to the circuit. This reduces the power consumption by a substantial percentage but there is still considerable power consumed by the current leakage through the low V.sub.t devices.
Therefore, there exists a need for a buffer circuit which receives a signal to enable and disable a memory circuit and operates to drive the power transfer transistors in such a manner that the leakage current through these transistors is reduced to essentially zero.